1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an analog semiconductor device.
2. Discussion of Related Art
An analog semiconductor device stores data of various states in contrary to a digital semiconductor device having data of low and high states. In the analog semiconductor device, a resistor and a capacitor are provided each node thereof. This capacitor includes a lower capacitor electrode, an insulating layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the insulating layer.
Referring to FIGS. 1A, 1B, 1C, a conventional method of manufacturing an analog semiconductor device will be described.
As shown in FIG. 1A, isolation films 2 are formed on a semiconductor substrate 1 and then gate insulating layer 3 and a first conductive layer 4 are formed thereon. An insulating layer 5 is formed on the first conductive layer 4 to act as a dielectric of a capacitor, and a second conductive layer 6 is then formed thereon. Next, a first photoresist pattern 7 is formed on the second conductive layer 6 by photolithography.
As shown in FIG. 1B, the second conductive layer 6 and the insulating layer 5 are etched by etching process using the first photoresist pattern 7 as an each mask, thus forming an upper capacitor electrode 6a. Next, the first photoresist pattern 7 is removed and a second photoresist layer 8 is coated on the entire surface of the substrate. As shown in FIG. 1C, the second photoresist layer 8 is patterned to form a second photoresist pattern 8a.
Afterward, although not shown in drawing, the first conductive layer 4 is etched by etching process using the second photoresist pattern 8a as an etch mask, thus patterning the gate and lower capacitor electrodes. Therefore, the gate is formed on the substrate between the isolation films 2, and capacitor are formed on the predetermined portion of the isolation films 2.
Meanwhile, as a design rule semiconductor devices decrease below half-micron, patterning conditions for the gate are difficult more and more. Therefore, if there is a little bit of a change in the patterning conditions, a critical dimension (CD) of the gate varies significantly. One of the main factors due to the CD variation of the gate is the thickness variation of the photoresist layer acting as a mask during patterning the gate. The thickness of the photoresist layer varies with the surface topology of underlayer. The thickness variation of the photoresist layer increases the CD variation of the gate.
In the conventional method of manufacturing the analog semiconductor device as described above, as shown in FIGS. 1B and 1C, the thickness of the second photoresist layer 8 varies since the surface topology property is deteriorated dud to the upper capacitor electrode 6a. Therefore, the CD variation of the gate increases. To overcome this problem, although the space between the gate and the capacitor is proposed to enhance the surface topology property, this decreases the integration of a semiconductor device.